This post shows how to analyze spectrum features, which is useful when running ADC/DAC simulations. Here is an example of an 8-bit DAC simulation. Plot the output analog signal (use the diff...

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Analog and Digital Co-Simulation in Cadence Environment Firstly, generate functional view and symbol for digital design Create a new cell in your design library with view “functional”, t...

This post is to show how to read data from file for simulation. Read decimal data from file and output directly when clock comes. Exmaple code: `include "constants.vams" `include "disciplines.v...

Tech. VDD Vov Vth 0.6um 5V 600mV 935mV 0.35um 3.3V 450mV 800mV 0.18um ...

This VerilogA block/code for Stop the current simulation in Cadence Virtuoso depending on analog conditions. This block is perfect when you need to perform multiple long simulations, for example, ...

如果仅用于快速模拟仿真用，SPI和dec2bin本质上是一样的。 1. 实现方案 可以通过以下两种方式实现 方案1：先移位后取余 先右移i位，再对2取余。 方案2：先取余后移位 先对2^(i+1)取余，再右移2^i-1位。 2. 实现方式 根据以上分析，显然第一个方案更直接。下面两种实现方式均以第一个方案为例。 用analogLib中vdc实现 可以通过一组理想源实现多位转换，第i...

电源完整性和噪声影响的分析 Simulation principle: Testbench is shown as follows. We need to run simulations in 3 steps: step 1. Transient sim to get the current waveform and save as a .vcsv file (this will...

This blog provides an example of bindkey setting to make specific layer(s) visible or not. Save the following script as layout.il, and load it in your .cdsinit by load("<path>/layout.il"). ...

OneDrive Client for Linux In this blog, I will list some key steps so you can use OneDrive client in Linux quickly. 1. Install For CentOS 7 user, follow this: Dependencies: Fedora < Versio...